Silicon Carbide Ushers In the 99% Era

For two decades, the workhorse of battery storage inverters—and power conversion systems (PCS) generally—was the silicon IGBT. It was rugged, cheap and well understood, but it forced engineers into a hard compromise: switch slowly enough to keep switching losses manageable, and accept bulky magnetics, or switch faster and watch efficiency collapse into heat. Silicon carbide MOSFETs break that trade-off. Their wider bandgap allows roughly a tenfold reduction in switching losses and much higher junction-temperature tolerance.
According to the National Renewable Energy Laboratory (NREL), SiC-based inverter designs can now reach 99% CEC-weighted efficiency in production hardware, up from roughly 96–97% for comparable silicon designs only a decade ago. Switching frequencies have climbed from the 3–10 kHz band into the 20–50 kHz range, which shrinks inductors and capacitors, raises power density and cuts the copper and steel content of a megawatt-scale PCS. The practical result is a smaller, lighter, cooler-running inverter delivering more kilowatt-hours per rack.
Gallium nitride is advancing in parallel, though its sweet spot remains lower-voltage applications—residential hybrid inverters, module-level electronics and DC optimisers—where its near-zero reverse-recovery charge matters most. At utility scale, SiC remains the dominant wide-bandgap choice, with Infineon, Wolfspeed, onsemi and STMicroelectronics all shipping automotive-qualified devices that storage OEMs have rapidly repurposed. Our overview of inverter technology covers how these topologies map onto residential and commercial platforms.

From Component to System: Where the Losses Actually Hide

A headline peak-efficiency figure is measured at one operating point, often at rated load and nominal DC voltage—conditions a battery rarely sees all day. Real assets spend much of their life at partial load, where conduction losses dominate and light-load efficiency becomes the binding constraint. This is why European Efficiency (EURO) and CEC weighting curves matter more than a marketing peak number, and why the industry has shifted to publishing weighted figures.
Losses break down roughly as follows in a modern two-stage PCS: around 45–55% conduction losses in the semiconductor devices, 30–40% switching losses, and the remainder split between gate drive, control electronics, magnetics and auxiliary cooling. SiC attacks the switching bucket directly and the conduction bucket partially, thanks to lower on-resistance per unit area. Three-level topologies—neutral-point-clamped and its advanced ANPC variant—further halve device voltage stress and improve harmonic quality, which reduces filtering losses.
The second stage, the DC/DC converter that manages battery voltage swing, is often overlooked. MPPT and DC/DC efficiency in leading hybrid platforms now exceeds 99.5% under EN 50530 testing, but the interaction between DC/DC setpoint and battery state of charge still creates measurable losses. Systems that dynamically optimise the DC bus voltage window, rather than fixing it, recover another fraction of a point. Our deep-dive on battery storage architecture explains how these stages are sequenced.

Round-Trip Economics: What One Percentage Point Is Worth

Round-trip efficiency is where inverter gains become money. An AC-coupled system typically loses 2–4 points to the extra DC–AC conversion; a DC-coupled architecture with a high-efficiency hybrid inverter can hold round-trip efficiency in the 92–95% range for LFP chemistry, versus 85–89% for older AC-coupled designs. BloombergNEF has documented global storage additions of roughly 69 GW/169 GWh in 2024, and at that scale a single percentage point of round-trip efficiency represents gigawatt-hours of otherwise-lost energy every year.
Run the arithmetic on a mid-size asset: a 100 MW/400 MWh LFP battery cycling once daily. One percentage point of round-trip efficiency equals 4 MWh per day, or about 1,460 MWh annually. Valued at a conservative $80–120/MWh of arbitrage spread, that is roughly $117,000–175,000 per year from the inverter alone—before accounting for reduced cooling load and longer equipment life. Across a 500 MW portfolio, the figure exceeds $700,000 annually.
The gains compound with degradation. Lower device losses mean lower junction temperatures, which in SiC MOSFETs can extend useful life by a factor of two or more compared with silicon devices pushed to similar thermal limits. That matters for 20-year asset models. It also reduces the parasitic cooling load, which itself consumes 1–3% of throughput in poorly designed liquid-cooled containers. Explore how these economics show up in delivered projects on our portfolio page.

Grid-Forming and the Efficiency Trade-Off

The industry's next requirement—grid-forming inverters that synthesise voltage and frequency rather than following the grid—introduces a genuine efficiency tension. Grid-forming control requires continuous headroom, fast current injection during faults (often 2–3 per unit for milliseconds) and virtual inertia emulation. Those capabilities demand larger semiconductor dies, bigger DC-link capacitance and higher switching reserves, all of which shave standing efficiency by 0.3–1.0 points depending on the operating mode.
IEEE 2800-2022 and Australia's AEMO requirements formalised much of this. AEMO's specification for new connecting batteries, informed by the operational record of the Hornsdale Power Reserve, effectively mandates grid-forming capability in several regions. Vendors have responded with dual-mode firmware: a maximum-efficiency grid-following mode for arbitrage and a grid-forming mode that activates when the system operator needs stability services, with the efficiency penalty shifting to the party that requests it.
That is a commercially significant shift. Where a storage owner bids both energy arbitrage and ancillary services, the inverter's ability to switch modes within milliseconds—without a full restart—determines whether the asset can stack revenues. System-level control, not just device physics, is now the frontier. Our technology overview tracks how these control layers are being integrated into modern PCS firmware.

Real-World Deployments and Vendor Benchmarks

The commercial evidence is no longer theoretical. Sungrow's PowerTitan liquid-cooled series and its latest utility PCS platforms publish maximum efficiency around 99%, with CEC-weighted figures in the 98.5% range. Tesla's Megapack line has progressively raised round-trip efficiency toward 92% at the DC block level through tighter integration of cells, DC/DC and inverter stages. Fluence, SMA and Huawei have all released wide-bandgap or hybrid-topology products citing meaningful gains over their own previous generations.
Fraunhofer ISE has demonstrated laboratory SiC inverter prototypes exceeding 99.5% efficiency, and its researchers have consistently argued that 99%-class conversion is the realistic ceiling for single-stage hardware—meaning further gains must come from architecture rather than components. Independent testing matters here: datasheet efficiency rarely survives third-party validation at partial load and elevated ambient temperature, which is why procurement teams increasingly specify weighted efficiency at 25 °C and 40 °C separately.
Battery chemistry is evolving alongside. LFP's flat voltage curve, while excellent for cycle life—see our lithium battery range—places more demand on the DC/DC stage to track the maximum power point across a wide state-of-charge window. Higher-voltage LFP packs and 1500 V DC architectures reduce current for a given power, cutting I²R losses in cabling and busbars by 25–40% compared with 1000 V designs.

What Comes Next: 2000 V DC and Smarter Silicon

The roadmap points in three directions. First, DC bus voltage is climbing from 1500 V to 2000 V, which reduces current and loss further but demands higher-rated SiC devices and reinforced insulation coordination. Second, hybrid SiC-plus-IGBT modules are emerging as a cost-effective middle path, using SiC for the fast-switching positions and silicon for slower, high-current paths.
Third, and potentially most , is the shift from device-level efficiency to system-level optimisation. Machine-learning-based control that predicts dispatch a day ahead and pre-positions the DC bus, adaptive switching frequency that varies with load, and bidirectional charging integrated directly into storage PCS are all entering pilot deployment. Each offers fractions of a point; together they could add another 1.5–2.5 points of round-trip performance by 2030.
For buyers, the practical advice is consistent: demand weighted efficiency data, not peak figures; test at realistic partial-load conditions; and model cooling parasitics explicitly. The efficiency breakthrough is real, but it is captured in procurement specifications and system architecture—not in a brochure headline. To discuss how these figures translate into a specific project, talk to our engineering team.